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FastContext: Training Efficient Repository Explorer for Coding Agents
Authors: Shaoqiu Zhang, Maoquan Wang, Yuling Shi, Yuhang Wang, Xiaodong Gu, Yongqiang Yao, Rao Fu, Shengyu Fu
Published: 2026-06-12 ...
arxiv:cs.SE
github-actions[bot]
Simulating Students Java Programming Errors with Large Language Models
Authors: Ali Keramati, Jie Cao, Iman Mohammadi, Mark Warschauer, Yang Shi Published: 2026-06-12 Categories: cs.SE, cs.CL
Links: ...
arxiv:cs.CL
arxiv:cs.SE
Problem
Only L2 (ridge) regularization exists; there is no L1/sparsity readout anywhere. Sparse readouts identify which
reservoir units / NG-RC monomials actually matter — essential for interpretability, ...
area:readouts
priority:P2
size:M
status:blocked
type:feature
El3ssar
Residual correlation PCA produces zero eigenvalue PC = no_of_items (rank deficiency). Truncate to no_of_items − 1
components.
bug
MarkElliott999
Preflight Checklist
- [x] I have searched existing issues and this hasn t been reported yet
- [x] This is a single bug report (please file separate reports for different bugs)
- [x] I am using the ...
area:installation
area:networking
bug
platform:linux
synced-from-upstream
shreyashjagtap157
Investigating Metamorphic Fuzz Oracle Enhancement via Large Language Models
Authors: Ruixiang Qian, Ding Yang, Zengxu Chen, Yuxuan Gao, Chunrong Fang, Chao Zhang, Zhenyu Chen Published: 2026-06-12
Categories: ...
arxiv:cs.CR
arxiv:cs.SE
Problem
Choosing the ridge alpha is the single biggest recurring pain in ESN practice. Today alpha is a fixed constructor scalar
with no automatic selection — the only path to a good value is the optional ...
area:readouts
priority:P1
size:M
status:blocked
type:feature
Evaluating LLMs for Obfuscation Detection and Classification in Android Apps
Authors: Luca Ferrari, Marco Alecci, Jordan Samhi, Tegawende F. Bissyande , Jacques Klein, Mariano Ceccato, Luca
Verderame ...
arxiv:cs.CR
arxiv:cs.SE
Proposal to improve performance
Hi team,
Qwen3-30B-A3B, TP4, 3500 in/1500 out, max-concurrency=8, request-rate=inf on 4090D
I noticed that in this scenario, the TTFT of graph mode is about 25% worse ...
performance
zhenwei-intel
环境
- SuperRTL v0.4.0, MCP stdio 模式, Windows 10
问题
generate_testbench 生成的 testbench 端口名全部变成了 wire（Verilog 关键字），代码完全不可编译。
复现
输入以下设计代码：
module riscv_alu (
input wire [31:0] op_a,
input wire ...
egg-rolls
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